Efficient and Programmable Processing Unit for H.264/AVC Systolic Unified Transform Engines

The H.264/AVC standard provides high compression efficiency at the cost of increased computational complexity. As a consequence, dedicated hardware circuits are typically required for its most computationally intensive parts, such as the transform coding block that must support multiple transform operations: the 4× 4 forward and inverse integer DCT and the 4×4 and 2×2 Hadamard transforms. In this paper, a simple and efficient programmable processing unit for the computation of all such transforms is proposed. This processing unit is highly suitable for systolic implementations of H.264/AVC unified transform engines using both 1-D and 2-D transform kernels. Experimental results obtained using a Xilinx Virtex-4 FPGA device demonstrate the superior performance and hardware efficiency levels provided by the proposed unit. Moreover, such results also reveal that transform engines based on the proposed processing unit can realize the above mentioned H.264/AVC transforms in real-time, for video sequences with resolutions up to UHDV.